1. Field of the Invention
The present invention relates to a differential amplifier suitable for power saving and a sampling and holding circuit using the same.
2. Description of the Related Art
The description will be given of a differential amplifier including a general MOS transistor having a planar-type structure. Respective gates of two MOS transistors being a differential pair are positive/negative inputs (differential inputs). Drains thereof are differential outputs. The sources of the two MOS transistors are connected with each other and a MOS transistor being a current source through its source and drain is inserted and connected between the sources of the two MOS transistors and a reference potential (ground or power supply voltage). Bias voltage is applied to a gate of the current source transistor, and this voltage suppresses common-mode gain and sets an output operating point to be a predetermined voltage. Further, normally, a MOS transistor (active load) to whose gate a predetermined bias voltage is applied is inserted and connected between the respective drains of the two MOS transistors and a reference potential (power supply voltage or ground) through its source and drain.
In the differential amplifier of the above-described structure in which the paths from source to drain are stacked vertically three times between the power supply voltage and the ground, the current source transistor and the transistors to be active loads as well as the pair of differential transistors are used in a saturation region (a region where a variation in drain current with respect to a variation in voltage between the source and the drain becomes sufficiently small). For this, when the voltage between gate and source is defined as Vgs and a threshold value is defined as Vth, the voltages Vds between the drains and sources of the respective vertically-stacked transistors are set to the voltage of Vgs−Vth or above. When the power supply voltage is defined as Vdd, then a maximum amplitude (peak to peak) Vo that the output signal can exhibit is Vo=Vdd−3 Vds.
Based on the relation: Vo=Vdd−3 Vds, when the power supply voltage downs in accordance with microfabrication of process, it is required that the amplitude of the output signal is reduced to enable all the transistors to operate in the saturation region.
For example, in the transistors having the same process, the case where the power source voltage is 1 V and the case where the power source voltage is 0.8 V are compared. Assuming that Vds is 0.2 V and when the power source voltage is 1 V, 0.2 V is ensured for the respective Vds of a current source transistor, a pair of differential transistors and active load transistors, then the voltage range of the output signal is 0.4 to 0.8V, as an example. Similarly, when the power source voltage is 0.8 V, the voltage range of the output signal is 0.4 to 0.6 V, as an example. In this manner, when the voltage of the power source downs from 1 to 0.8 V, the possible voltage range (namely, amplitude) of the output signal is reduced by half in this case.
When the signal amplitude is small, in order to obtain a desired SNR (signal-to-noise-ratio), it is necessary to reduce a noise level, requiring much more bias current for the transistors as a result thereof. For instance, in the case of the differential amplifier used in a pipeline A/D converter and the like, when the signal amplitude becomes a half, then fourfold current is required to obtain the same SNR. This is because the operation is a sampling system, in which the noise electric power follows kT/C (C: sampling frequency, k=Boltzmann constant, T=temperature).
Even when the power supply voltage reduces by 20%, when fourfold current is required, the consumption power increases. The comparisons are made between the same processes in the above, however, in actual, it is conceivable that the parasitic capacitance reduces and the same performance can be obtained from smaller bias current along with progress in the process. However, when the power supply voltage reduces to around 1 V, the fact that the signal amplitude cannot be obtained sufficiently affects largely, and in the case of an analog circuit such as a differential amplifier, the microfabrication of the process not always leads to the power saving of the circuit.
Note that, in a differential amplifier having MOS transistors and dealing with differential inputs and differential outputs, generally, a circuit to suppress common-mode signals and to set the output operating point of the differential pair to a predetermined level is required. For this purpose, a common-mode feedback circuit is used. An output operating point is generally set at a midpoint of the operating range to obtain a dynamic range as large as possible. The common-mode feedback circuit is composed of a circuit detecting a common-mode voltage of output terminals and an error amplifier comparing and amplifying the detected voltage relatively to a reference voltage (Vref) corresponding to a desired voltage as an output. The output of the error amplifier is connected to the gate of the current source transistor. With this, feedback is applied so that the output midpoint voltage comes equal to Vref.
As an example of the circuit detecting the common-mode voltage in the common-mode feedback circuit as described above, there is one disclosed in JP-A 2000-148262. Since a detection circuit is connected to the output terminals, generally it causes output impedance to lower, so that DC gain is caused to lower. In this disclosed circuit, the same structure as the structure to the output terminals is newly provided for inputs into the detection circuit to prevent the output impedance of the output terminals from lowering.
Subsequently, a structure of a general MOS transistor will be described hereinafter. Currently MOS transistors are largely of a planar type in which a single gate controls a channel. Along with the microfabrication, however, leak current between the drain and the source has been closely looked as a problem. This current is useless current leaking via a silicon substrate even when no voltage is applied to between the gate and the source. As a cause thereof, a phenomenon called punch through, out of short-channel effects, is related thereto.
On the other hand, it is known that the structure controlling the channel by plural gates can bring about an effect of suppressing the punch-through. That having two gates is called Dual-gate FinFET and that having three gates is called Tri-gate MOSFET. Out of the transistors with two gates, that can control the two gates separately is disclosed in “CMOS Vertical Multiple Independent Gate Field Effect Transistor (MIGFET); Mathew, L. et. al.; SOI Conference, 2004. Proceedings. 2004 IEEE International; 4-7 Oct. 2004 Page(s): 187-189”. In the disclosure, it is further stated that the second gate can vary the threshold voltage.